In integrated circuit (IC) design, static timing analysis (STA) is used to predict the performance of an IC and to verify that the IC, as designed, will function correctly. Specifically, STA is used to predict the arrival times (ATs) of clock and data signals and the results can be compared against established timing requirements (e.g., required arrival times (RATs)) to see if the integrated circuit will function properly with a sufficiently high probability. As IC designs become more and more complex, performing STA on the top-level design (also referred to herein as the full design) of an IC is no longer a viable option due to the large runtime and memory requirements for completing the analysis. Consequently, IC designers have turned to a hierarchical approach to designing ICs and performing STA. With a hierarchical approach to design, multiple different design blocks are developed, STAs are performed on the design blocks and, based on the results of the STAs, timing abstracts for the different design blocks are generated. A timing abstract for a specific design block only contains relevant timing information required for interfacing with other design blocks at a higher level of hierarchy or in the top-level design and, particularly, periphery timing information and does not include internal timing information. In any case, during design, an IC designer will select design blocks and, then, interconnect the selected design blocks with top-level logic. Typically, the resulting top-level design will include multiple instances of the exact same design block at different locations within the IC. The timing abstracts for the selected design blocks are subsequently used to analyze an overall timing model for the full top-level design, thereby reducing the runtime and memory requirements for completing the analysis. Although this hierarchical approach has its advantages, the use of the multiple instances of the same design block requires that the block be designed to meet the highest performance requirements which can result in more performance than needed in areas that do not require as much performance. This results in more power and area consumption than in the case where hierarchical blocks are not used.